package org.shalicon.chip
package utils

import chisel3._
import chisel3.util.{Decoupled, DecoupledIO, Valid}

class FrontendReq(implicit p: Parameter) extends ShBundle()(p) {
  val pc = UInt(VADDR_WIDTH)
  val speculative = Bool()
}

class FrontendResp(implicit p: Parameter) extends ShBundle()(p) {
  val pc = UInt(VADDR_WIDTH) // for ID use
  val data = Vec(p.fetch_count, UInt(INST_WIDTH))
  val mask = Bits(p.fetch_count.W)
  val fetch_exception = Bool() // todo
  val fetch_replay = Bool()
}

// note: ready-valid signals

class FrontendIO(implicit p: Parameter) extends ShBundle()(p) {
  val req = Valid(new FrontendReq())
  val resp = Flipped(Decoupled(new FrontendResp()))
}
